@T4V0@kbin.social

Estudante de engenharia eletrônica

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You know what moment has always bugged me in Star Trek Enterprise?

I’m always bugged more by individual moments than bigger things. So while T’Pol might be wearing an old fun center carpet as a uniform, and the temporal Cold War is both overly complex and excruciatingly boring neither of those things bothers me more than the following....

T4V0, (edited )
@T4V0@kbin.social avatar
  • insist on not having a unit of exchange or currency, but then some how having massive amounts of trade and economy.

As you mentioned before, they have replicators, so why would they have currency inside the Federation?

They don't need money in the Federation, but since they have limited resources on a spaceship and also interact with other species, they kinda have to barter, mostly to curry favor with these species.

T4V0,
@T4V0@kbin.social avatar

They have trade. Inside and outside.

Outside sure, but I don't think I have seen any internally. Do you have examples?

Currency facilitates trade. Next question: why do they need trade? (Besides cultural exports- let’s…. Not get into that.)

They can just replicate the other's civilization money if it is at a lower stage of technology advancement. In the scenario of the same or later technology stage, like the Ferengi Alliance, they would trade for technology, information and/or territories.

The one resource they have a desperate need is dilithium, which they had automated the extraction using the Doctor holograms lol.

T4V0, (edited )
@T4V0@kbin.social avatar

the trouble with tribbles grain deal comes to mind. The grain is being held/shipped for a member world.

Being shipped doesn't mean it is a trade deal, they offered assistance due to its strategic position as it is a disputed planet between the Federation and the Klingons. And if you're talking about the deal between the bartender and Cyrano Jones, he is independent from the Federation, like Quark's bar, any deal between would be external (and they seem to use credits as a currency?).

Then there’s Cassidy Yates and all the federation traders in ds9 (though that’s not a solid argument.) there’s also the cargo ships frequently used in tng as background.

In a similar situation, Deep Space Station 9 is close to disputed territory and Federation candidate members. So again, they deal between Federation and others species. And the cargo ships in TNG aren't necessarily, doing any sort trade, they may simply hauling supplies for Federation planets and colonies.

Dilithium deuterium minning are also frequently mentioned… usually the federation being interested in minning for its own use. (Just another reason to build the power system off something else…actually.)

Since they need it for every warp drive spaceship, I assume it would be a very well controlled resource. And due to its importance I don't think they would hire external help, so it would be fair to assume they use Federation miners and scientists to extract it. But again I don't think they mention any internal trade, so I assume they distribute it accordingly to each species or organization.

dejo, (edited ) to science Serbian

Hi, I'm not quite sure if this vhdl code and testbench is correct for the given task. Can you take a look?

Design a one-hour kitchen timer. The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm. Realize the task using the software package Quartus or in GHDL, confirm the correctness of the project task by simulation.

This is VHDL code:

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Kitchen_Timer is
  port (
    clk   : in std_logic;    -- Clock input
    reset : in std_logic;    -- Reset input
    start : in std_logic;    -- Start button input
    stop  : in std_logic;    -- Stop button input
    alarm : out std_logic    -- Alarm output
  );
end entity Kitchen_Timer;

-- Declare the architecture for the kitchen timer
architecture Behavioral of Kitchen_Timer is
  signal count     : integer range 0 to 3600 := 0;   -- Counter for timer
  signal alarming  : std_logic := '0';               -- Signal to indicate alarming interval
  signal alarm_en  : std_logic := '0';               -- Signal to enable alarming interval
  signal alarm_cnt : integer range 0 to 600 := 0;    -- Counter for alarming interval
begin
  -- Process to control the kitchen timer and alarming interval
  process (clk, reset)
  begin
    if (reset = '1') then
      count     <= 0;
      alarming  <= '0';
      alarm_en  <= '0';
      alarm_cnt <= 0;
    elsif (rising_edge(clk)) then
      if (stop = '1') then
        count     <= 0;
        alarming  <= '0';
        alarm_en  <= '0';
        alarm_cnt <= 0;
      elsif (start = '1' and count < 3600) then
        count <= count + 1;
        if (count = 3600) then
          count     <= 0;
          alarming  <= '0';
          alarm_en  <= '0';
          alarm_cnt <= 0;
        elsif (count > 0) then
          alarm_en <= '1';
        end if;
      end if;

      if (alarm_en = '1') then
        if (alarm_cnt < 600) then
          alarm_cnt <= alarm_cnt + 1;
        else
          alarm_cnt <= 0;
          alarming  <= '1';
        end if;
      end if;
    end if;
  end process;

  -- Assign the alarm output
  alarm <= alarming;
end architecture Behavioral; ```


This is Testbench:

```library ieee;
use ieee.std_logic_1164.all;

entity tb_Kitchen_Timer is
end tb_Kitchen_Timer;

architecture tb of tb_Kitchen_Timer is

    component Kitchen_Timer
        port (clk   : in std_logic;
              reset : in std_logic;
              start : in std_logic;
              stop  : in std_logic;
              alarm : out std_logic);
    end component;

    signal clk   : std_logic;
    signal reset : std_logic;
    signal start : std_logic;
    signal stop  : std_logic;
    signal alarm : std_logic;

    constant TbPeriod : time := 1000 ns; -- EDIT Put right period here
    signal TbClock : std_logic := '0';
    signal TbSimEnded : std_logic := '0';

begin

    dut : Kitchen_Timer
    port map (clk   => clk,
              reset => reset,
              start => start,
              stop  => stop,
              alarm => alarm);

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

    -- EDIT: Check that clk is really your main clock signal
    clk <= TbClock;

    stimuli : process
    begin
        -- EDIT Adapt initialization as needed
        start <= '0';
        stop <= '0';

        -- Reset generation
        -- EDIT: Check that reset is really your reset signal
        reset <= '1';
        wait for 100 ns;
        reset <= '0';
        wait for 100 ns;

        -- EDIT Add stimuli here
        wait for 100 * TbPeriod;

        -- Stop the clock and hence terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;

end tb;

-- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is
    for tb
    end for;
end cfg_tb_Kitchen_Timer;```

 #science

T4V0, (edited )
@T4V0@kbin.social avatar

@dejo I don't think this is going to work properly. If I understood correctly your alarm is going to start "alarming" (maybe ringing would be a better term here) after 10 minutes and reset an hour later. I also don't see a way to input or select the desired time for it to ring.

I would also change the stop signal to be the same as the reset (lookup alias) and remove the synchronous stop inside the main process. And the testbench is incomplete since it nevers starts nor its timer is set.

T4V0,
@T4V0@kbin.social avatar

@dejo

can you send me the code with the modifications so that I know what exactly you mean?

I would rather not, as it isn't a good learning experience for you, and would require some time for me to write the code.

Though if you have any questions about my previous answer, feel free to ask me about it.

As a freebie for you, pay attention to the alarming signal, and the condition that has been set: "The device should have buttons/switches to start and stop the timer, as well as to set the desired time interval for the alarm.". If I wanted the alarm to ring after 50 minutes, how would I do that? And what happens when the timer starts?

From the code I see here, the alarm is going to ring 10 minutes after being started, and it won't stop until an hour passes. And it has no way to set a time for it to ring, it always rings after 10 minutes.

And, not only that, the start signal is never set in the testbench, so the timer is never going to begin.

T4V0, (edited )
@T4V0@kbin.social avatar

@dejo This is much better, but there is still some room for improvement.

There is a mismatch between your comparisons count and alarm_interval. Here in the code bellow you can see the issue:

if stop = '1' or count = alarm_interval then

count <= 0; -- count is 0 here

end if;

[...]

alarming <= '1' when count >= alarm_interval else '0'; -- This condition is never true due to count always being 0 or smaller the alarm_interval.
alarm <= alarming;


As it is right now, the alarming signal is never going to be '1'. It is best to split the comparison and write to alarming directly:

if stop = '1' then

count <= 0;
alarming <= '0';

end if;

if count = alarm_interval then

alarming <= '1';

end if;

[...]

alarm <= alarming;


As for the testbench, you should set the start and unset it only after the alarming is '1', and test if alarming is working after adjusting the timer:

stimuli : process

begin

-- Reset generation

reset <= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

reset <= '0';

-- Add your stimuli and test cases here

-- For example:

start <= '1';
stop <= '0';

wait for 620 us; -- Wait until alarm is alarming

start <= '0'
stop <= '1';
adjust_interval_up <= '1';

wait for 1 us; -- Increment the timer by a minute

start <= '1';
stop <= '0';
adjust_interval_up <= '0';

wait for 1220 us; -- Wait until the alarm is alarming

start <= '0';
stop <= '1';
adjust_interval_down <= '1';

wait for 1 us; -- Decrement the timer by a minute

start <= '1';
stop <= '0';
adjust_interval_down <= '0';

wait for 620 us; -- Wait until the alarm is alarming

start <= '0';
stop <= '1';

wait for 20 us;

-- ...

-- Stop the clock and hence terminate the simulation

TbSimEnded <= '1';

wait;

end process;

I suggest changing the 100 ms time slices you use in the timer to a minute instead. That way your simulation time could be much quicker (though you would also have to change the testbench delays).

T4V0,
@T4V0@kbin.social avatar

@dejo I have made a few changes to your code:

Kitchen_Timer.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Kitchen_Timer is
    port
    (
        clk                  : in std_logic; -- Clock input
        reset                : in std_logic; -- Reset input
        start                : in std_logic; -- Start button input
        stop                 : in std_logic; -- Stop button input
        adjust_interval_up   : in std_logic; -- Button for increasing alarm interval
        adjust_interval_down : in std_logic; -- Button for decreasing alarm interval
        alarm                : out std_logic -- Alarm output
    );
end entity Kitchen_Timer;
architecture Behavioral of Kitchen_Timer is
    signal count          : integer range 0 to 60 := 0; -- Adjust range for 1 hour
    signal alarming       : std_logic             := '0';
    signal alarm_interval : integer range 1 to 60 := 1; -- Adjust range for 1 hour
begin
    process (clk, reset)
    begin
        if reset = '1' then
            count          <= 0;
            alarm_interval <= 1;
        elsif rising_edge(clk) then
            if start = '1' then
                count <= count + 1;
            end if;
            if stop = '1' then
                count    <= 0;
                alarming <= '0';
            end if;
            if count = alarm_interval then
                alarming <= '1';
            end if;
            if adjust_interval_up = '1' then
                if alarm_interval < 60 then
                    alarm_interval <= alarm_interval + 1; -- Adjust increment for 1 minute
                end if;
                count <= 0; -- Reset count when adjusting interval
            elsif adjust_interval_down = '1' then
                if alarm_interval > 60 then
                    alarm_interval <= alarm_interval - 1; -- Adjust decrement for 1 minute
                end if;
                count <= 0; -- Reset count when adjusting interval
            end if;
        end if;
    end process;
    alarm <= alarming;
end architecture Behavioral;

tb_Kitchen_Timer.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_Kitchen_Timer is
end tb_Kitchen_Timer;

architecture tb of tb_Kitchen_Timer is
    signal clk                  : std_logic := '0';
    signal reset                : std_logic := '0';
    signal start                : std_logic := '0';
    signal stop                 : std_logic := '0';
    signal adjust_interval_up   : std_logic := '0';
    signal adjust_interval_down : std_logic := '0';
    signal alarm                : std_logic;
    constant TbPeriod           : time      := 10 ns;
    signal TbClock              : std_logic := '0';
    signal TbSimEnded           : std_logic := '0';
begin
    dut : entity work.Kitchen_Timer
    port map
    (
        clk                  => clk,
        reset                => reset,
        start                => start,
        stop                 => stop,
        adjust_interval_up   => adjust_interval_up,
        adjust_interval_down => adjust_interval_down,
        alarm                => alarm
    );

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

    -- EDIT: Check that clk is really your main clock signal
    clk <= TbClock;

    stimuli : process
        variable num_ticks : natural;
    begin
        -- Reset generation
        reset <= '1';
        wait for 20 ns;
        reset <= '0';
        wait for 20 ns;
        -- Start the timer
        start <= '1';
        wait for 20 ns;
        start <= '0';
        stop  <= '1';
        -- Adjust interval up and down
        adjust_interval_up <= '1';
        wait for 10 ns;
        start              <= '1';
        stop               <= '0';
        adjust_interval_up <= '0';
        wait for 30 ns;
        start                <= '0';
        stop                 <= '1';
        adjust_interval_down <= '1';
        wait for 10 ns;
        start                <= '1';
        stop                 <= '0';
        adjust_interval_down <= '0';
        wait for 20 ns;
        start              <= '0';
        stop               <= '1';
        adjust_interval_up <= '1';
        wait for 600 ns;
        start              <= '1';
        stop               <= '0';
        adjust_interval_up <= '0';
        -- Wait for the timer to reach the alarm interval (60 clocks)
        wait for 600 ns; -- Simulate for the required time
        -- Stop the timer
        start <= '0';
        stop  <= '1';
        wait for 100 ns;
        -- Stop the clock and terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;
end tb;

This should be easier to simulate, I've included a simulation done with Questa.

T4V0,
@T4V0@kbin.social avatar

@dejo

What do you think about the specifications that the project requires, should I stick to your code or should I add something from my own code?

I would stick to my code, your alarm isn't going to work properly due to its comparisons as I mentioned in my previous comments. But if you want to improve the code I modified, you can change the adjust_interval_up and adjust_interval_down buttons to be synchronized to their own states rather than the clock (make their own process with their signals added to the signal sensitivity list and add an extra asynchronous condition to zero the counter on the original process). If you don't make a change like this your alarm is going to take up to an hour to adjust its timer range.

Does your simulation correspond to a time of 1 hour and should there be alarming on the simulation?

Yes, if you have a 1/60 Hertz clock signal. And you must have alarming on the simulation as it is crucial to show that it works.

T4V0,
@T4V0@kbin.social avatar

@dejo

Is the 1/60 Hz set somewhere or is it set in the code itself?

You would set that on the testbench or on your synthesis code, but that is unnecessary, I only said that in case if you tested it on a actual FPGA. If you do that on your testbench, it would take a very long time to simulate.

When you say that I must have an "alarming" signal on the simulation, is it actually this "alarm" signal that is presented on the simulation or?

The alarm signal. The "alarming" is when the alarm signal is in a high logic state.

And, do I need to have count signal in simulation?

I wouldn't say it's mandatory, but it is a good addition to the simulation, keep it.

T4V0,
@T4V0@kbin.social avatar

@dejo In your .do script file add this line:

add wave -label "count" -radix unsigned /dut/Kitchen_Timer/count

T4V0,
@T4V0@kbin.social avatar

@dejo No, the alarm signal takes a longer time to start rather than the interval when it's set.

You seem to have some trouble picturing the Kitchen Timer itself.

Kitchen timer

Here, when you change the time interval it's the same as when you turn the knob. So it doesn't last longer when you increase the timer, it just takes longer for it to activate.

T4V0,
@T4V0@kbin.social avatar

@dejo Whoops, I made a mistake, you don't need to include the entity when simulating. This line bellow should be the correct one:

add wave -label "count" -radix unsigned /dut/count

This is my .do file (when using Modelsim or Questa, change to the directory with all the .vhd files and the .do file and execute the command do tb.do):

tb.do

#Creates project's library
vlib work

#Compiles project with VHDL93 standard: all files used in the testbench. They should be compiled in order of dependency.
vcom -93 Kitchen_Timer.vhd testbench.vhd

#Simulates (work is the directory, tb_Kitchen_Timer is the entity's name).
#The argument -voptargs="+acc" is necessary to disable signal optimization in Questa.
vsim -voptargs="+acc" -t ns work.tb_Kitchen_Timer

#Show waveforms.
view wave

#Add specific signals.
# -radix: binary, hex, dec, unsigned.
# -label: wave's name.
add wave -label "clk" -radix binary /clk
add wave -label "reset" -radix binary /reset
add wave -label "start" -radix binary /start
add wave -label "stop" -radix binary /stop
add wave -label "adjust_interval_up" -radix binary /adjust_interval_up
add wave -label "adjust_interval_down" -radix binary /adjust_interval_down
add wave -label "alarm" -radix binary /alarm
add wave -label "count" -radix unsigned /dut/count
add wave -label "TbClock" -radix binary /TbClock
add wave -label "TbSimEnded" -radix binary /TbSimEnded

#Simulate for 1500 ns.
run 1500ns

# Zoom to fit entire window.
wave zoomfull
write wave wave.ps

I've also included the simulation result.

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